This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-345298, filed Dec. 3, 1999; and No. 2000-006706, filed Jan. 14, 2000, the entire contents of which are incorporated herein by reference.
(1) Background 1
The present invention relates to contact structures in semiconductor devices such as a semiconductor memory and the like, and more particularly to contact structures in a non-volatile semiconductor memory (for example, a bit line contact structure, a source line contact structure and the like).
As an example of conventional non-volatile semiconductor memories, a NAND cell type flash memory will be described below in terms of its device structure.
A NAND cell type flash memory has a memory cell array comprised of a plurality of NAND cell units. Each of the NAND cell units is comprised of a plurality of memory cells connected in series and a pair of select transistors, each connected to both ends of the NAND cell unit. The select transistors are connected between a bit line and a source line.
Each of the memory cells comprises an n-channel MOS transistor having a so-called stacked gate structure in which a control gate electrode is stacked on a floating gate electrode. Each of the select transistors comprises an n-channel MOS transistor having a structure similar to the memory cell, i.e., a structure in which an upper electrode is stacked on a lower electrode. However, it is, for example, the lower electrode which actually functions as a gate electrode of the select transistor.
In two adjacent transistors of the plurality of transistors within a NAND cell unit (memory cells, select transistors), one source region or one drain region is shared by these two transistors.
In the following, a specific structure of the NAND cell type flash memory will be described.
FIG. 1 is a circuit diagram illustrating a portion of a memory cell array in the NAND cell type flash memory.
A NAND cell unit is comprised of a plurality (four, eight, 16 or the like) of memory cells connected in series, and a pair of select transistors, each connected to one of both ends of the NAND cell unit. Also, the NAND cell units are connected between bit lines BL0, . . . , BL63 and source lines SL. The source lines SL are connected to reference potential lines (wirings for shunting) formed of a conductive material such as aluminum, polysilicon or the like, at predetermined locations.
The source lines SL extend in a row direction, while the bit lines BL0, . . . , BL63 and the reference potential lines extend in a column direction. Contact sections of the source lines SL with the reference potential lines are provided, for example, each time the source lines SL intersect 64 bit lines BL0, . . . , BL63. The reference potential lines are connected to a so-called peripheral circuit arranged around the memory cell array.
Word lines (control gate lines) WL1, . . . , WLn extend in the row direction, and select gate lines SG1, SG2 also extend in the row direction. A set of memory cells connected to a single word line (control gate line) WLi is called a page. Also, a set of memory cells connected to the word lines WL1, . . . , WLn sandwiched between the two select gate lines SG1, SG2 is called a NAND block or simply a block.
One page is comprised, for example, of 256 bytes (256xc3x978) of memory cells. The memory cells within one page are written substantially at the same time. Also, when one page is comprised of 256 bytes of memory cells with one NAND cell unit comprised of eight memory cells, one block is comprised of 2,048 bytes (2048xc3x978) of memory cells. The memory cells within one block are erased substantially at the same time.
FIG. 2 is a top plan view illustrating the device structure of one NAND cell unit within the memory cell array. FIG. 3 is a cross-sectional view taken along the line IIIxe2x80x94III in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line IVxe2x80x94IV in FIG. 2. FIG. 5 in turn illustrates an equivalent circuit of the device of FIGS. 2 through 4.
A p-type substrate (p-sub) 11-1 is formed therein a so-called double well region which comprises an n-type well region (Cell n-well) 11-2 and a p-type well region (Cell p-well) 11-3. Memory cells and select transistors are formed in the p-type well region 11-3.
Memory cells and select transistors are arranged within an element area within the p-type well region 11-3. The element area is surrounded by an element isolation oxide film (element isolation area) 12 formed on the p-type well region 11-3.
In this example, as illustrated in FIG. 5, one NAND cell unit is comprised of eight memory cells M1-M8 connected in series, and a pair of select transistors S1, S2, each of which is connected to one of both ends of the NAND cell unit.
Each of the memory cells is comprised of a silicon oxide film (gate insulating film) 13 formed on the p-type well region (Cell p-well) 11-3; a floating gate electrode 141, 142, . . . , 148 on the silicon oxide film 13; a silicon oxide film (interpoly insulating film) 15 on the floating gate electrodes 141, 142, . . . , 148; a control gate electrode 161, 162, . . . , 168 on the silicon oxide film 15; and source/drain regions 19 within the p-well region (Cell p-well) 11-3.
Each of the select transistors in turn is comprised of the silicon oxide film (gate insulating film) 13 formed on the p-type well region 11-3; gate electrodes 149, 1410 or 169, 1610 on the silicon oxide film 13; and source/drain regions 19, 19(S), 19(D) within the p-well region 11-3.
The structure of the select transistors is similar to the structure of the memory cells, as appreciated from the foregoing. This is because the memory cells and the select transistors are simultaneously formed in the same process to reduce the number of steps involved in the process and accordingly reduce the manufacturing cost.
The memory cell differs from the select transistors in structure in the following aspects.
As illustrated in FIG. 6, in regard to the memory cells, a floating gate electrode 141, . . . , 148 is provided for each of memory cells, the control gate electrodes 161, . . . , 168 extend on the memory cell array linearly in the row direction, and contact sections W for the control gate electrodes 161, . . . , 168 are provided at ends of the control gate electrodes 161, . . . , 168 in the row direction.
On the other hand, in regard to the select transistors, the gate electrodes 149, 1410 as lower electrodes, for example, are provided in common to a plurality of select transistors in the row direction, and contact sections SS, SD for the gate electrodes 149, 1410 are provided at regular intervals on the memory cell array.
Turning back to description on FIGS. 2 through 5, one set of source/drain regions (n+-type diffusion layers) 19 is shared by two adjacent transistors of a plurality of transistors (memory cells, select transistors) within the NAND cell unit.
The memory cells and the select transistors are overlain by a silicon oxide film (CVD oxide film) 17 formed by a CVD (chemical vapor deposition) method. A bit line 18 is routed on the CVD oxide film 17. The bit line 18 is connected to one end of the NAND cell unit, i.e., the n+-type diffusion layer 19(D) through a contact plug 20.
In a non-volatile semiconductor memory including the NAND cell-type flash memory as descried above, researches and developments for miniaturization and higher integration of memory cells are under progress in order to increase the memory capacity (the number of bits) in one chip.
However, to achieve the miniaturization and higher integration of memory cells, problems associated therewith must be solved to achieve an improved reliability. The problems involved in the miniaturization and higher integration include an increase in wiring resistance and contact resistance, problems related to the manufacturing processes (for example, a problem resulting from a seam which occurs when a conductive material is buried in miniature holes), and the like.
(2) Background 2
The present invention relates to a non-volatile semiconductor memory device, and more particularly to improvements in a cell layout for a high density and high integration non-volatile semiconductor memory device.
Non-volatile semiconductor memory devices which can electrically rewrite data are widely used for high speed ROM and mass storage. Also, memory cells in a non-volatile semiconductor memory device are generally comprised of MOS transistors. Structures generally employed for the memory cell are a stacked gate structure which has a charge transfer layer and a control gate layer, and a single gate structure comprised only of a control gate layer.
FIGS. 7 through 9 illustrate an example of a memory cell which has the stacked gate structure. FIG. 7 is a top plan view of the memory cell; FIG. 8 is a cross-sectional view taken along the line VIIIxe2x80x94VIII in FIG. 7; and FIG. 9 is a cross-sectional view taken along the line IXxe2x80x94IX in FIG. 7.
In this example, the memory cell comprises an N-channel MOS transistor. In this case, the memory cell is formed in a P-type silicon substrate or in a P-type well region. In this example, however, the memory cell is formed in the P-type well region.
Specifically, an N-well region 12 and a P-well region 13 are formed in the P-type silicon substrate 11. The silicon substrate 11 is also formed with trenches for element isolation, and an insulating material (for example, silicon oxide) 14 for element isolation is buried in the trenches.
An area sandwiched by the element isolation insulating materials 14 serves as an element area. A thin tunnel insulating film (for example, made of silicon oxide) 15 is formed on the silicon substrate 11 (P-well region 13) in the element area such that a micro-tunnel current can be applied therethrough during writing/erasing operations.
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is made of an electrically floating conductive layer (for example, a polysilicon layer including impurities).
A control gate layer 18 is formed on the charge transfer layer 16 through an intergate insulating layer 17. Since the charge transfer layer 16 is capacitively coupled to the control gate layer 18, variations in potential on the control gate layer 18 cause like variations in potential on the charge transfer layer 16.
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-alignment, their side edges are in alignment with each other in a direction (column direction) perpendicular to a direction (row direction) in which the control gate layer (word lines) 18 extends. Also, the side edge of the charge transfer layer 16 in the row direction exists on the element isolation insulating material 14.
In the element area, a surface area of the silicon substrate 11 beneath the charge transfer layer 16 serves as a channel region. N-type diffusion layers (a source region or a drain region) 19 are also formed on both sides of the channel region.
In the memory cell having the foregoing stacked gate structure, data for the memory cell is determined by the amount of charges in the charge transfer layer 16. Specifically, a threshold value for the memory cell becomes higher as negative charges (electrons) are increased in the charge transfer layer 16 and lower as positive charges (holes) are increased in the charge transfer layer 16.
A state in which the charge transfer layer 16 includes a large amount of negative charges is called a writing state, while a state in which the charge transfer layer 16 includes a large amount of positive charges is called an erasing state.
The amount of charges within the charge transfer layer 16 can be adjusted by applying a tunnel current to the tunnel insulating layer 15 during writing/erasing operations. Whether the tunneling current flows or not is determined by a voltage applied between the control gate layer (charge transfer layer) and the channel. Specifically, a high voltage applied to the tunnel insulating film 15 causes the tunnel current to flow.
For example, when the tunnel insulating film 15 is applied with a high voltage and the potential on the channel is higher than the potential on the charge transfer layer, the tunnel current flows from the channel to the charge transfer layer 16. On the other hand, when the tunnel insulating film 15 is applied with a high voltage and the potential on the charge transfer layer 16 is higher than the potential on the channel, the tunnel current flows from the charge transfer layer 16 to the channel.
FIGS. 10 through 12 illustrate an example of a memory cell having the single gate structure. FIG. 10 is a top plan view of the memory cell; FIG. 11 is a cross-sectional view taken along the line XIxe2x80x94XI in FIG. 10; and FIG. 12 is a cross-sectional view taken along the line XIIxe2x80x94XII in FIG. 10.
In this example, the memory cell also comprises an N-channel MOS transistor. In this case, the memory cell is formed in a P-type silicon substrate or in a P-type well region. In this example, however, the memory cell is formed in the P-type well region.
Specifically, a P-type silicon substrate 21 is formed therein with an N-well region 22 and a P-well region 23. The silicon substrate 21 is also formed with trenches for element isolation, and an insulating material for element isolation (for example, silicon oxide) 24 is buried in the trenches.
An area sandwiched between the element isolation insulating materials 24 serves as an element area. A thin tunnel insulating film (for example, made of silicon oxide) 25 is formed on the silicon substrate 21 (P-well region 23) in the element area such that a micro-tunnel current can be applied therethrough during writing/erasing operations.
A charge holding insulating layer 26 is formed on the tunnel insulating film 25 for holding charges and preventing the charges from leaking. The charge holding insulating layer 26 is formed, for example, of a plurality of insulating materials arranged in stack.
A control gate layer 27 is formed on the charge holding insulating layer 26. Also, in the element area, a surface area of the silicon substrate 21 beneath the control gate layer 27 serves as a channel region. N-type diffusion layers (a source region or a drain region) 28 are also formed on both sides of the channel region.
In the memory cell having the foregoing single gate structure, data for the memory cell is determined by the amount of charges which are trapped at a charge trap level formed on an interface between the tunnel insulating film 25 and the charge holding insulating layer 26. Specifically, a threshold value of the memory cell becomes higher as the amount of negative charges (electrons) trapped at the charge trap level is increased, and lower as the amount of positive charges (holes) trapped at the charge trap level is increased.
A state in which a large amount of negative charges is trapped at the charge trap level is called a writing state, while a state in which a large amount of positive charges is trapped at the charge trap level is called an erasing state.
The amount of charges at the charge trap level formed on the interface between the tunnel insulating film 25 and the charge holding insulating film 26 can be adjusted by applying a tunnel current to the tunnel insulating film 25 during writing/erasing operations. Whether the tunnel current flows or not is determined by a voltage applied between the control gate layer and the channel. Specifically, when the tunnel insulating film 25 is applied with a high voltage, the tunnel current flows.
For example, when the tunnel insulating film 25 is applied with a high voltage, and the potential on the channel is higher than the potential on the control gate layer, the tunnel current flows from the channel to the charge holding insulating layer 26. On the other hand, when the tunnel insulating layer 25 is applied with a high voltage, and the potential on the control gate layer 27 is higher than the potential on the channel, the tunnel current flows from the charge holding insulating layer 26 to the channel.
It should be noted that for the memory cell in the single gate structure, a charge transfer insulating layer may be provided between the tunnel insulating film 25 and the charge holding insulating layer 26 to determine a state of the memory cell (data) based on the amount of charges trapped in the charge transfer insulating layer.
FIGS. 13 through 16 illustrate a memory cell array of a NOR cell type non-volatile semiconductor memory device. FIGS. 13 and 14 are top plan views of the memory cell array; FIG. 15 is a cross-sectional view taken along the line XVxe2x80x94XV in FIGS. 13 and 14; and FIG. 16 is a cross-sectional view taken along the line XVIxe2x80x94XVI in FIGS. 13 and 14.
It should be noted that for facilitating the understanding of the figures, FIG. 13 omits a wiring layer in which bit lines are formed, and FIG. 14 shows only the wiring layer in which the bit lines are formed. In other words, the bit lines shown in FIG. 14 are formed on the device of FIG. 13.
While description on this example is focused on a memory cell array comprised of memory cells in the stacked gate structure, a similar layout may be employed with memory cells in the single gate structure, as a matter of course.
Since the structure of the memory cell has been described in connection with FIGS. 7 through 9, repetitive description thereon is omitted.
A control gate layer (word lines) 18 of memory cells extend in a row direction. An interlayer insulating film (made, for example, of silicon oxide) 31 is formed on the memory cells for overlying the memory cells. The interlayer insulating layer 31 is formed with contact holes (bit line contacts) 30 which reach a drain diffusion layer 19d of the memory cells.
A contact plug 32 made of a conductive material is buried in each of the contact holes 30. Then, bit lines 33 are formed on the interlayer insulating film 31. The bit lines 33 are electrically connected to the drain diffusion layers 19d of the memory cells through respective contact plugs 32.
The bit lines 33 extend in a column direction. Specifically, the control gate layer 18 and the bit lines 33 are arranged such that they intersect perpendicular or generally perpendicular to each other. One memory cell is provided at each of intersections of the control gate layer 18 with the bit lines 33.
The drain diffusion layers 19d are shared by two memory cells in the column direction, and independent of each other for memory cells in the row direction. A source diffusion layer 19s extends in the row direction, and serves as a common source line. Therefore, the source diffusion layer 19s is shared not only by two memory cells in the column direction but also by a plurality of memory cells in the low direction adjacent to the source diffusion layer 19s. 
In a region in which the source diffusion layer 19s is formed, no element isolation insulating material 14 is formed. In other words, the element isolation areas (element isolation insulating materials) 14, which are formed extending in the column direction, are interrupted by the source diffusion layer 19s. Also, the drain diffusion layers 19d of memory cells existing in one column are electrically connected to each other through the bit line 33.
FIGS. 17 and 18 show the shape of contact holes (bit line contacts) when the device illustrated in FIGS. 13 through 16 is actually manufactured.
Specifically, as memory cells are miniaturized and contact holes (bit line contacts) are also miniaturized, even if the contact holes are laid out in the shape of square, a resist film serving as a mask is circular in shape, resulting in formation of circular contact holes which are caused by etching with the circular resist film used as a mask.
It should be noted that this example is intended to explain that the contact holes may be formed not only in the shape of square but also in the shape of circle.
FIGS. 19 through 22 illustrate a memory cell array of a NAND cell type non-volatile semiconductor memory device. FIGS. 19 and 20 are top plan view of the memory cell array; FIG. 21 is a cross-sectional view taken along the line XXIxe2x80x94XXI in FIGS. 19 and 20; and FIG. 22 is a cross-sectional view taken along the line XXIIxe2x80x94XXII in FIGS. 19 and 20.
It should be noted that for facilitating the understanding of the figures, FIG. 19 omits a wiring layer in which bit lines are formed, and FIG. 20 shows only the wiring layer in which the bit lines are formed. In other words, the bit lines shown in FIG. 20 are formed on the device of FIG. 19.
While description on this example is focused on a memory cell array comprised of memory cells in the stacked gate structure, a similar layout may be employed with memory cells in the single gate structure, as a matter of course.
The memory cell array of the NAND cell type has a structure in which a plurality of NAND strings (or NAND cell units) are connected to bit lines. One NAND string is comprised of a plurality of memory cells connected in series, and a pair of select transistors, each of which is connected to one of both ends of the NAND string.
Since the structure of the memory cell has been described in connection with FIGS. 7 through 9, repetitive description thereon is omitted. The stacked gate structure is employed for the select transistors in a manner similar to the memory cells. However, the select transistors do not have a charge transfer layer, and for example, have an upper gate and a lower gate connected to each other to function as a single gate electrode (select gate line) SG1 or SG2.
A control gate layer (word line) 18 and the select gate lines SG1, SG2 of memory cells extend in a row direction. An interlayer insulating film (made, for example, of silicon oxide) 31 is formed on the memory cells for overlying the memory cells. The interlayer insulating layer 31 is formed with contact holes (bit line contacts) 30 which reach a drain diffusion layer 19d of the memory cells.
A contact plug 32 made of a conductive material is buried in each of the contact holes 30. Then, bit lines 33 are formed on the interlayer insulating film 31. The bit lines 33 are electrically connected to the drain diffusion layers 19d of the memory cells through respective contact plug 32.
The bit lines 33 extend in a column direction. Specifically, the control gate layer 18 and the bit lines 33 are arranged such that they intersect perpendicular or generally perpendicular to each other. One memory cell is provided at each of the intersections of the control gate layer 18 with the bit lines 33.
In the NAND string, two adjacent transistors (memory cells, select transistors) share a single diffusion layer 19. Also, the drain diffusion layer 19d positioned closest to the bit line 33 in the NAND string is shared by two NAND strings in the column direction, however, the drain diffusion layers 19d are independent of each other for NAND strings in the row direction. The source diffusion layer 19s extends in the row direction, and serves as a common source line. Therefore, the source diffusion layer 19s is shared not only by two NAND strings in the column direction but also by a plurality of NAND strings in the row direction adjacent to the source diffusion layer 19s. 
Also, in a region in which the source diffusion layer 19s is formed, no element isolation insulating material 14 is formed. In other words, the element isolation areas (element isolation insulating materials) 14, which are formed extending in the column direction, are interrupted by the source diffusion layer 19s. Also, the drain diffusion layers 19d of NAND strings existing in one column are electrically connected to each other through the bit line 33.
FIGS. 23 and 24 show the shape of contact holes (bit line contacts) when the device illustrated in FIGS. 19 through 22 is actually manufactured.
Specifically, as memory cells are miniaturized and contact holes (bit line contacts) are also miniaturized, even if the contact holes are laid out in the shape of square, a resist film serving as a mask is circular in shape, resulting in formation of circular contact holes which are caused by etching with the circular resist film used as a mask.
It should be noted that this example is intended to explain that the contact holes may be formed not only in the shape of square but also in the shape of circle.
The NOR cell type and NAND cell type non-volatile semiconductor memory devices have been described above. In either of the structures, the contact holes (bit line contacts) 30 are arranged in a line in the row direction.
This is because memory cells can be laid out in the highest density when the element areas and the element isolation areas alternately arranged in the row direction extend in the column direction and the control gate layers extend in the row direction orthogonal to the element areas. In other words, the employment of such a layout causes the contact holes (bit line contacts) 30 to be necessarily arranged in a line in the row direction.
In this case, as illustrated in FIGS. 13, 14, 19 and 20, the contact holes (bit lines contacts) 30 are equally spaced at a constant pitch (or a constant period) Xpitch. Then, this constant pitch Xpitch is equal to a repeating pitch (or a repeating period) Xi+Xe of the element areas and the element isolation areas alternately arranged in the row direction. This is because the contact holes are gradually deviated from drains of cells unless both the pitches are the same.
Here, the element areas and the element isolation areas alternately arranged in the row direction are repetitions of so-called lines (element areas or the silicon substrate 11) and spaces (element isolation areas or STI (Shallow Trench Isolation)), wherein the repeating pitch (or the repeating period) Xi+Xe can be reduced in accordance with the performance of an exposure apparatus and processing techniques.
The contact holes (bit line contacts) 30 are formed by opening holes through an interlayer insulating film made of silicon dioxide (SiO2) or the like. The holes having a small diameter cannot be formed satisfactorily. Conversely, the holes having a large diameter cause narrow spacings between adjacent holes, resulting in difficulties in processing.
Therefore, unlike a repeating period of lines and spaces determined by exposure processing techniques, the pitch Xpitch of the contact holes (bit line contacts) 30 is determined not only by the exposure processing techniques but also by the size of the contact holes 30 themselves and the spacings between the contact holes 30.
Also, the contact holes (bit line contacts) 30 are shaped in square (after manufacturing, they may be transformed into circular holes). It is known that square holes are more difficult than a line and space pattern in miniaturization from a viewpoint of the processing techniques. Specifically, even if a reduction in size of memory cells enables the realization of a narrower repeating pitch Xi+Xe of the element areas and the element isolation areas, the contact holes 30 themselves cannot be reduced in size, resulting in the inability of narrowing the pitch Xpitch (repeating pitch Xi+Xe of the element areas and the element isolation areas) of the contact holes (bit line contacts) 30.
As appreciated from the foregoing, in the prior art, the contact holes (particularly, bit line contacts), because of their square shape, encounter difficulties in miniaturization thereof. This gives rise to a problem that the repeating pitch Xi+Xe of the element areas and the element isolation areas (equal to the pitch of the bit lines) is limited to the pitch Xpitch of the contact holes, so that a higher density of memory cells cannot be accomplished.
(1) Summary 1
It is an object of the present invention to provide a semiconductor device which has a novel device structure for solving a problem of increased wiring resistance and contact resistance as well as problems possibly arising in manufacturing processes in order to realize miniaturization and higher integration of memory cells.
A semiconductor device according to the present invention includes a contact plug buried in a contact hole and having an upper portion protruding from the contact hole, and
a wiring in contact with the contact plug, made of a material different from a material of which the contact plug is made, wherein the contact plug extends through the wiring, and the contact plug has an upper surface substantially coplanar with an upper surface of the wiring.
A manufacturing method of a semiconductor device according to the present invention includes the steps of forming a contact hole through an insulating film having a planar upper surface, burying a contact plug in the contact hole, wherein the contact plug has an upper surface substantially coplanar with an upper surface of the insulating film, forming a wiring groove in the insulating film, overlapping the contact hole, and forming a wiring in the wiring groove such that the wiring has an upper surface substantially coplanar with the upper surface of the contact plug.
A semiconductor device according to the present invention includes an element area arranged between element isolation areas, and a metal film arranged on the element area, and having end portions buried in a contact hole overlapping the element isolation area and in a wiring groove on the contact hole. In the element area, memory cells are formed, and the contact hole is arranged on a diffusion layer in the element area.
A semiconductor device according to the present invention includes a bit line contact section for connecting a memory cell to a bit line, a word line contact section for a word line, a gate contact section for a gate of a MOS transistor in a peripheral circuit section, a diffusion layer contact section for a diffusion layer of the MOS transistor in the peripheral circuit section, and a well contact section for on a well region, wherein the bit line contact section has a contact structure substantially identical to a contact structure of at least one of the word line contact section, the gate contact section, the diffusion layer contact section and the well contact section.
A semiconductor device according to the present invention includes a bit line contact section for connecting a NAND cell unit to a bit line, a source line contact section for connecting the NAND cell unit to a source line, a word line contact section for a word line, gate contact sections for a gate of a MOS transistor in a peripheral circuit section and for a gate of a select transistor, a diffusion layer contact section for a diffusion layer of the MOS transistor in the peripheral circuit section, and a well contact section for a well region, wherein the bit line contact section, the source line contact section, the word line contact section, the gate contact sections, the diffusion layer contact section, and the well contact section are all substantially identical in contact structure.
A semiconductor device according to the present invention includes first and second element areas arranged between element isolation areas, a first contact section arranged on the first element area and formed of a conductive film buried in a contact hole, an end portion of which overlaps the element isolation area, and a second contact section arranged on the second element area and formed of a conductive film buried in a contact hole, an end portion of which does not overlap the element isolation area, wherein the first and second contact sections have substantially the same contact structure.
A manufacturing method of a semiconductor device according to the present invention includes the steps of forming a stopper film on first and second conductive layers, forming a first insulating film on the stopper film, etching the first insulating film on condition that the first insulating film has no selectivity to the stopper film to form a first contact hole reaching the first conductive film and a second contract hole not reaching the second conductive layer through the first insulating film, etching the first insulating film on condition that the first insulating film has an etching selectivity to the stopper film to extend the second contact hole such that a bottom of the second contact hole reaches the stopper film, removing the stopper film exposed on the bottom of the contact hole, and filling the same material in the first and second contact holes.
(2) Summary 2
It is an object of the present invention to modify the shape of contact holes to reduce the pitch of the contact holes, i.e., a repeating pitch of element areas and element isolation areas (equal to a pitch of bit lines) to accomplish a higher density, a larger capacity and a reduced cost of memory cells.
A non-volatile semiconductor memory device according to the present invention includes element areas and element isolation areas repeatedly arranged in one direction at a regular period, memory cells arranged in the element areas, contact holes arranged in the one direction at the same period as the regular period, and a wiring arranged in the contact holes for communicating data with the memory cells, wherein the contact holes have a width in a second direction orthogonal to the first direction larger than a width of the contact hole in the first direction.
A non-volatile semiconductor memory device according to the present invention includes element areas and element isolation areas repeatedly arranged in one direction at a regular period, memory cells arranged in the element areas, first contact holes arranged in the one direction generally at the same period as the regular period; a bit line arranged in the first contact holes and connected to one end of a current path of each memory cell through at least one transistor, second contact holes arranged in the one direction generally at the same period as the regular period, and a source line arranged in the second contact holes and connected to the other end of the current path of each memory cell through at least one transistor, wherein both the first and second contact holes have a width in a second direction orthogonal to the first direction larger than a width in the first direction.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.